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r01ds0228ej0060 rev.0.60 page 1 of 51 nov 14, 2014 rz/t1 group preliminary datasheet specifications in this docume nt are tentative and subject to features on-chip 32-bit arm cortex-r4f processor ? high-speed realtime control with maximum operating frequency of 450/600 mhz capable of 747/996 dmips (in operation at 450/600 mhz) ? on-chip 32-bit arm cort ex-r4f (revision r1p4) ? tightly coupled memory (tcm) with ecc: 512 kbytes/32 kbytes ? instruction cache/data cache with ecc: 8 kbytes per cache ? high-speed interrupt ? the fpu supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at single- precision and double-precision. ? harvard architecture with 8-stage pipeline ? supports the memory protection unit (mpu) ? arm coresight architecture, includes support for debugging through jtag and swd interfaces on-chip 32-bit arm cortex-m3 processor (in products incorporating an r-in engine) ? 150-mhz operating frequency ? on-chip 32-bit arm cort ex-m3 (revision r2p1) ? risc harvard architecture with 3-stage pipeline ? supports the memory protection unit (mpu) low power consumption ? standby mode, sleep mode, and module stop function on-chip extended sram ? up to 1 mbyte of the on-chip extended sram with ecc ? 150 mhz data transfer ? dmac: 16 channels 2 units ? dmac for the ethernet controller: 1 channel event link controller ? module operations can be started by event signals rather than by interrupt handlers. ? linked operation of modules is available even while the cpu is in the sleep state. reset and power supply voltage control ? four reset sources including a pin reset ? dual power-voltage configuration: 3.3 v (i/o unit), 1.2 v (internal) clock functions ? external clock/oscillator input frequency: 25 mhz ? cpu clock frequency: up to 450/600 mhz ? low-speed on-chip oscillator (loco): 240 khz independent watchdog timer ? operated by a clock signal obtained by frequency-dividing the clock signal from the low-speed on-chip oscillator: up to 120 khz safety functions ? register write protection, input clock oscillation stop detection, crc, iwdta, and a/d self-diagnosis ? an error control module is incorporated to generate a pin signal output, interrupt, or internal reset in response to errors originating in the various modules. security functions (optional)* 2 ? boot mode with security through encryption encoder interfaces (optional)* 3 ? endat 2.2 and biss-compliant interfaces various communications interfaces ? ethernet - ethercat slave controller: 2 port s (for products incorporating an r-in engine) - ether-mac: 1 port (without the switching function) or - ether-mac: 1 port (2 ports with the switching function) ? usb 2.0 high-speed host/function : 1 channel ? can (compliant with iso118 98-1): 2 channels (max.) ? scifa with 16-byte transmission and reception fifos: 5 channels ? i 2 c bus interface: 2 channels for transfer at up to 400 kbps ? rspia: 4 channels ? spibsc: provides a single interface for multi-i/o compatible serial flash memory external address space ? buses for high-speed data transfer at 75 mhz (max.) ? support for up to 6 cs areas ? 8-, 16-, or 32-bit bus space is selectable per area up to 33 extended-function timers ? 16-bit tpua (12 channels), mtu3a (9 channels), gpta (4 channels): input capture, output compare, pwm waveform output ? 16-bit cmt (6 channels), 32-bit cmtw (2 channels) serial sound interface (1 channel) ? interface ? up to 4 ? modulators are connectable externally. 12-bit a/d converters ? 12 bits 2 units (max.) (8 channels for unit 0; 16 channels for unit 1) ? self diagnosis ? detection of analog input disconnection temperature sensor for measuring temperature within the chip general-purpose i/o ports ? 5-v tolerance, open drain, input pull-up multi-function pin controller ? the locations of input/output functions for peripheral modules are selectable from among multiple pins. operating temperature range ? tj = -40c to +125c prbg0320ga-a 1717mm, 0.8-mm pitch plqp0176ld-a 20 x 20mm, 0.4-mm pitch 450 mhz/600mhz, mcu with arm cortex?-r4f and -m3* 1 , on-chip fpu, 747/996 dmips, up to 1 mbyte of on-chip extended sram, ethernet mac, ethercat* 1 , usb 2.0 high-speed, can, various communications interfaces such as an spi multi-i/o bus controller, ? interface, safety functions, encoder interfaces* 1 , and security functions* 1 r01ds0228ej0060 rev.0.60 nov 14, 2014 note 1. optional note 2. details of these optional functions will only be given after completion of a binding non-disclosure agreement. for detai ls, contact our sales representative. note 3. for details, contact our sales representative.
r01ds0228ej0060 rev.0.60 page 2 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 1. overview 1.1 outline of specifications this lsi circuit is a high-performan ce mcu equipped with the arm cortex ?-r4f processor and cortex-m3 (for products incorporating an r-in engine) processors, and in corporating integrated peripheral functions necessary for system configuration. table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different packages. table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package. for details, see table 1.2 , comparison of functions for different packages. table 1.1 outline of specifications (1 / 7) classification module/function description cpu central processing unit (cortex-r4f) ? maximum operating frequency 320-pin fbga: 600 mhz 176-pin hlqfp: 450 mhz ? 32-bit cpu cortex-r4f design ed by arm (core revision r1p4) ? address space: 4 gbytes ? instruction cache: 8 kbytes (with ecc with) ? data cache: 8 kbytes (with ecc with) ? tightly coupled memory (tcm) atcm: 512 kbytes (with ecc with) btcm: 32 kbytes (with ecc with) ? instruction set: armv7-r architecture, so support includes thumb and thumb-2 ? data arrangement instructions: little endian data: little endian ? memory protection unit (mpu) central processing unit (cortex-m3) (for products incorporating an r-in engine) ? operating frequency: 150 mhz ? 32-bit cpu cortex-m3 designed by arm (core revision r2p1) ? address space: 4 gbytes ? instruction set: armv7-r architecture, so support includes thumb? and thumb-2 ? data arrangement instructions: little endian data: little endian ? memory protection unit (mpu) fpu (cortex-r4f) ? supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at single- and double-precision. ? registers 32-bit single-word registers: 32 bits 32 (can be used as 16 double-word registers: 64 bits x 16) memory on-chip extended sram with ecc ? capacity: up to 1 mbyte ? 150 mhz ? sec-ded (single error correction/double error detection) operating modes ? three boot modes spi boot mode (for booting up from serial flash memory) 16-bit bus boot mode (nor flash) 32-bit bus boot mode (nor flash) clock clock generation circuit ? the input clock can be selected from an exte rnal clock signal or external resonator. ? detection of input clock oscillation stopping ? the following clocks are generated. cpu clock: 450/600 mhz (max.) system clock: 150 mhz (fixed) high-speed peripheral module clock: 150 mhz (fixed) low-speed peripheral module clock: 75 mhz (fixed) adcclk in the 12-bit a/d converter (s12adc): 60 mhz (max.) external bus clock: 75 mhz (max.) low-speed on-chip oscillator: 240 khz (fixed) reset res # pin reset, error control module (ecm) reset, software reset
r01ds0228ej0060 rev.0.60 page 3 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. low power low power consumption ? standby mode (cortex-r4f) ? sleep mode (cortex-m3) (for products incorporating an r-in engine) ? module stop function interrupt cortex-r4f vector interrupt controller (vic) ? peripheral function interrupts: 272 sources / 274 sources (for products incorporating an r-in engine) ? external interrupts: 20 sources (nmi, irq0 to irq15, eth0_int, eth1_int, and eth2_int pins) ? software interrupts: 1 source ? non-maskable interrupts: 2 sources ? sixteen levels specifiable for the order of priority cortex-m3 nested-type vector interrupt controller (nvic) (only included in products incorporating an r-in engine) ? peripheral function interrupts: 82 sources ? external interrupts: 19 sources (irq0 to irq15, eth0_int, eth1_int, and eth2_int pins) ? software interrupts: 1 source ? non-maskable interrupts: 1 source ? sixteen levels specifiable for the order of priority external bus extension bus state controller (bsc) ? the external address space is divided into six areas (cs0 to cs5) for management. ? the following features settable for each area independently. bus size (8, 16, or 32 bits): available sizes depend on the area. number of access wait cycles (different wa it cycles can be specified for read and write access cycles in some areas) idle wait cycle insertion (between same ar ea access cycles or different area access cycles) specifying the memory to be connected to each area enables direct connection to sram, sram with byte selection, sdra m, and burst rom (clocked synchronous or asynchronous). the address/data multiplexed i/o (mpx) interface is also available. ? outputs a chip select signal (cs0# to cs5#) according to the target area (cs assert or negate timing can be selected by software) ? sdram refresh auto refresh or self-refresh mode selectable ? sdram burst access data transfer direct memory access controller (dmac) ? 2 units (16 channels for uni t 0, 16 channels for unit 1) ? transfer modes: single transfer mode and block transfer mode ? transfer size unit 0: 1/2/4/16/32/64 bytes unit 1: 1/2/4/16 bytes ? activation sources: software trigger, exte rnal dma requests (dreq0 to dreq2), external interrupts, and interrupt requests from peripheral functions i/o ports general-purpose i/o ports ? 320-pin fbga i/o pins: 209 input pins: 9 pull-up/pull-down resistors: 209 open-drain outputs: 9 5-v tolerance: 9 ? 176-pin hlqfp i/o pins: 97 input pins: 5 pull-up/pull-down resistors: 97 open-drain outputs: 5 5-v tolerance: 5 event link controller (elc) ? 87 event signals can be interlinked with the operation of modules. ? in particular, the operation of timer modul es can be started by input event signals. ? event-linked operation of signals of ports b and e is to be possible. multi-function pin controller (mpc) the locations of input/ outp ut functions are selectable from among multiple pins. table 1.1 outline of specifications (2 / 7) classification module/function description
r01ds0228ej0060 rev.0.60 page 4 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. timers 16-bit timer pulse unit (tpua) ? (16 bits 6 channels) 2 units* 1 ? maximum of 32 pulse-input/output possible ? select from among seven or eight c ounter-input clock signals for each channel (with maximum operating frequency of 75 mhz) ? input capture/output compare function ? counter clear operation (synchronous clearing by compare match/input capture) ? simultaneous writing to multiple timer counters (tcnt) ? simultaneous register input/output by synchronous counter operation ? output of pwm waveforms in up to 15 phases in pwm mode ? support for buffered operation, phase-counting mode (two phase encoder input) and cascade-connected operation (32 bits 2 channels) depending on the channel. ? ppg output trigger can be generated ? capable of generating conversion start triggers for the a/d converters ? digital noise filtering of sign als from the input capture pins ? event linking by the elc multifunction timer pulse unit (mtu3a) ? 9 channels (16 bits 8 channels, 32 bits 1 channel) ? maximum of 28 pulse-input/output and 3 pulse-input possible ? select from among 9, 11, or 12 c ounter-input clock signals for each channel (with maximum operating frequency of 150 mhz) ? input capture function ? 39 output compare/input capture registers ? counter clear operation (synchronous clearing by compare match/input capture) ? simultaneous writing to multiple timer counters (tcnt) ? simultaneous register input/output by synchronous counter operation ? buffered operation ? support for cascade-connected operation ? automatic transfer of register data ? pulse output mode toggle/pwm/complementary pw m/reset-synchronized pwm ? complementary pwm output mode outputs non-overlapping waveforms for controlling 3-phase inverters automatic specification of dead times pwm duty cycle: selectable as any value from 0% to 100% delay can be applied to r equests for a/d conversion. non-generation of interrupt requests at p eak or trough values of counters can be selected. double buffer configuration ? reset synchronous pwm mode three phases of positive and negative pwm waveforms can be output with desired duty cycles. ? phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2) ? counter functionality for dead-time compensation ? generation of triggers for a/d converter conversion ? a/d converter start triggers can be skipped ? digital noise filter function for signals on t he input capture and external counter clock pins ? ppg output trigger can be generated ? event linking by the elc table 1.1 outline of specifications (3 / 7) classification module/function description
r01ds0228ej0060 rev.0.60 page 5 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. timers general pwm timer (gpta) ? 16 bits 4 channels ? counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels ? select from among four counter-input clock signals for each channel (with maximum operating frequency of 150 mhz) ? 2 input/output pins per channel ? 2 output compare/input capture registers per channel ? for the 2 output compare/input capture r egisters of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. ? in output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically pwm waveforms. ? registers for setting up frame intervals on each channel (with c apability for generating interrupts on overflow or underflow) ? synchronizable operation of the several counters ? modes of synchronized operation (synchroni zed, or displaced by desired times for phase shifting) ? generation of dead times in pwm operation ? through combination of three counters, generation of automatic three-phase pwm waveforms incorporating dead times ? starting, clearing, and stopping counters in response to external or internal triggers ? internal trigger sources: software, and compare-match ? generation of triggers for a/d converter conversion ? digital noise filter function for signals on t he input capture and external trigger pins ? event linking by the elc programmable pulse generator (ppg) ? (4 bits 4 groups) 2 units* 1 ? pulse output with the mtu3a or tpua output as a trigger ? maximum of 32 pulse-output possible compare match timer (cmt) ? (16 bits 2 channels) 3 units ? select from among four counter-input clock signals for each channel (with maximum operating frequency of 75 mhz) ? event linking by the elc compare match timer w (cmtw) ? (32 bits 1 channel) 2 units ? compare-match, input-capture input, and output-comparison output are available. ? select from among four counter-input clock signals for each channel (with maximum operating frequency of 75 mhz) ? interrupt requests can be output in response to compare-match, input-capture, and output-comparison events. ? digital noise filter function fo r signals on the input capture pins ? event linking by the elc watchdog timer (wdta) ? 14 bits 1 channel products incorporating an r-in engine: 14 bits 2 channels ? select from among six counter-input cloc k signals for each channel (with maximum operating frequency of 75 mhz) independent watchdog timer (iwdta) ? 14 bits 1 channel ? counter-input clock: low-speed on-chip oscillator (loco)/2 ? dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 (with maximum operating frequency of 120 mhz) port output enable 3 (poe3) ? control of the high-impedance state of the mtu3a / gpta's waveform output pins ? 4 pins for input from signal sources: poe0, poe4, poe8, poe10 ? initiation on detection of short-circuited out puts (detection of simultaneous pwm output to the active level) ? initiation by input clock oscillation- stoppage detection, pll oscillation anomaly detection, or software ? additional programming of output control target pins is enabled table 1.1 outline of specifications (4 / 7) classification module/function description
r01ds0228ej0060 rev.0.60 page 6 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. communication function ethernet mac (etherc) ? 1 port ? ieee802.3 is supported ? 10base and 100base are supported ? full duplex and half duplex are supported ? automatic pause packet transmission function ? auto broadcast suspension functi on by the pause packet reception ? mii/rmii interface is supported ethernet switch ? 2-port phy interfaces ? ieee802.3 ? 10base, 100base ? full and half duplex ? hardware switching, lookup, and filtering ? qos with frame prioritization ? priority control based on vlan priority (ieee802.1q), which enables priority reassignment ? classification and priority assignment based on ipv4 diffserv code point field, ipv6 class of service ? queue with four priority levels ? multicasting and broadcasting ? vlan frame ? ieee1588 timer module ? cut-through and hub features ? device level ring (dlr) ethercat slave controller (ecatc) * 2 ? 1 channel (2 ports) * 3 ? ethercat slave controller ip core (made by beckhoff automation gmbh) implemented usb 2.0 hs host/ function module ? 1 port ? compliance with the usb 2.0 specification ? transfer rate high speed (480 mbps), full speed (12 mbps) ? communications buffer incorporates 1 kbyte of ram for host mode incorporates 8 kbytes of ram for function mode serial communication interface with fifo (scifa) ? 5 channels ? serial communications modes: asynchronous, clock synchronous ? on-chip baud rate generator allows selection of the desired bit rate ? choice of lsb-first or msb-first transfer ? both the transmission and reception sectio ns are equipped with 16-byte fifo buffers, allowing continuous transmission and reception. ? bit rate modulation i 2 c bus interface (riica) ? 2 channels i 2 c bus format supports the multi-master max. transfer rate: 400 kbps ? event linking by the elc can module (rscan) ? 2 channels ? compliance with the iso11898-1 specific ation (standard frame and extended frame) ? message buffers max. 64 x 2 channels of receive mess age buffers, which are used by all channels 16 transmit message buffers per channel ? max. transfer rate: 1 mbps table 1.1 outline of specifications (5 / 7) classification module/function description
r01ds0228ej0060 rev.0.60 page 7 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. communication function serial peripheral interface (rspia) ? 4 channels ? rspi transfer facility using the mosi (master out slave in), miso (master in slave out), ssl (slave select), and rspck (rspi clock) signals enables se rial transfer through spi operation (four lines) or clock-synchronous operation (three lines) capable of handling serial transfer as a master or slave ? data formats switching between msb first and lsb first the number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or re ceived in a single transfer operation (with each frame having up to 32 bits) ? buffered structure double buffers for both transmission and reception ? rspck can be stopped automatically with the receive buffer full for master reception ? event linking by the elc spi multi i/o bus controller (spibsc) ? 1 channel ? one serial flash memory with multiple i/o bus sizes (single/dual/quad) can be connected. ? external address space read mode (built-in read cache) ? spi operating mode ? clock polarity and clock phase can be selected. ? maximum transfer rate: 300 mbps (for quad) serial sound interface (ssi) ? 1 channel ? duplex communication ? support of various serial audio formats ? support of master and slave functions ? generation of programmable word clock and bit clock ? support of 8, 16, 18, 20, 22, 24, and 32-bit data formats ? support of eight-stage fifo for transmission and reception ? support of ws continue mode in wh ich the ssiws signal is not stopped. ? interface (dsmif) ? 4 channels ? up to 4 ? modulators are externally connectable ? sync filter can be selected as first, second or third order 12-bit a/d converter (s12adc) ? 12 bits 2 units (unit 0: 8 channels, unit 1: 16 channels)* 1 ? 12-bit resosultion ? conversion time unit 0: 0.6 s per channel unit 1: 2.0 s per channel ? operating mode scan mode (single scan mode, cont inuous scan mode, or group scan mode) group a priority control (only for group scan mode) ? sample-and-hold function common sample-and-hold circuit included in addition, channel-dedicated sample-and-hol d function (4 channels: in unit 0 only) included ? sampling variable sampling time can be set up for each channel ? self-diagnostic function the self-diagnostic function internally generates three analog input voltages (unit 0: vrefl0, vrefh0 1/2, vrefh0; unit 1: vrefl1, vrefh1 1/2, vrefh1) ? double trigger mode (a/d conversion data duplicated) ? detection of analog input disconnection ? three ways to start a/d conversion software trigger, timer (mtu3a, gpta, tpua) trigger, external trigger ? event linking by the elc temperature sensor ? 1 channel ? relative precision: 1c ? the voltage of the temperature is convert ed into a digital value by the 12-bit a/d converter (unit 0). table 1.1 outline of specifications (6 / 7) classification module/function description
r01ds0228ej0060 rev.0.60 page 8 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. note 1. one unit for 176-pin devices (only unit 0 is provided) note 2. ethercat is a registered trademark of beckhoff automati on gmbh, germany.this controller is only included in products incorporating an r-in engine. note 3. not included in 176-pin devices. note 4. see figure 1.3, list of products, for the products that have the secure boot mode. detail s of these optional functions w ill only be given after completion of a binding non-disclosure agr eement. for details, contact our sales representative. note 5. for details, contact our sales representative. safety register write protection function protects important registers from being over written for in case a program runs out of control. crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-, 16-, or 32-bit units ? select any of four generating polynomials: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 (32- ethernet), x 16 + x 12 + x 5 + 1 (16-ccitt), x 8 + x 4 + x 3 + x 2 + 1 (8-saej1850), x 8 + x 5 + x 3 + x 2 + x + 1 (8-0x2f) input clock oscillation stop function input clock oscillation stop detection: available clock monitor circuit (clma) monitors the abnormal output clock frequency fr om the pll circuit or low-speed on-chip oscillator. data operation circuit (doc) the function to compare, add, or subtract 16-bit data error control module (ecm) ? generates an interrupt, internal reset, or erro r output for the error signal input from each module. ? time-out function ? the error output is duplicated in the master and the checker. security secure boot mode* 4 as an option, a boot mode with encryption as a security function is available. encoder interfaces* 5 endat 2.2 and biss-compliant interfaces power supply voltage vdd = pllvdd0 = pllvdd1 = dvdd_usb = 1.14 to 1.26 v vccq33 = avcc0 = avcc1 = vrefh0 = vrefh1 = vdd33_usb = 3.0 to 3.6 v operating temperature tj = -40 to +125c package 320-pin fbga: 17 17 mm, 0.8-mm pitch prbg0320ga-a 176-pin hlqfp: 20 20 mm, 0.4-mm pitch plqp0176ld-a debugging interface ? coresight architecture designed by arm ? debugging function by the jtag/swd interfac e, and trace function by the trace port/ swv interface table 1.1 outline of specifications (7 / 7) classification module/function description
r01ds0228ej0060 rev.0.60 page 9 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. note 1. see table 1.3, list of products for the products that hav e the secure boot mode. details of these optional functions wil l only be given after completion of a binding non-disclosure agr eement. for details, contact our sales representative. note 2. for details, contact our sales representative. table 1.2 comparison of functions for different packages module/function rz/t1 group 320 pins 176 pins r-in engine incorporated r-in engine not- incorporated external bus external bus width 32 bits interrupt external interrupt nmi, irq0 to irq15, eth0_int, eth1_int, eth2_int nmi, irq0 to irq15, eth0_int, eth1_int dma dma controller (dmac) ch0 to ch31 timers 16-bit timer pulse unit (tpua) ch0 to ch11 (unit 0, unit 1) ch0 to ch5 (unit 0) multi-function timer pulse unit 3 (mtu3a) ch0 to ch8 general-purpose pwm timer (gpta) ch0 to ch3 port output enable 3 (poe3) available programmable pulse generator (ppg) unit 0, unit 1 unit 0 compare match timer (cmt) ch0 to ch5 compare match timer w (cmtw) ch0, ch1 watchdog timer (wdta) ch0, 1 ch0 independent watchdog timer (iwdta) available communicatio n function ethernet controller (etherc) 3 ports 2 port ethercat slave contoller (ecatc) a vailable not supported not supported usb 2.0 hs host/function module (usb) ch0 serial communications interface with fifo (scifa) ch0 to ch4 i 2 c bus interface (riica) ch0, ch1 serial peripheral interface (rspia) ch0 to ch3 can module (rscan) ch0, 1 spi multi i/o bus controller (spibsc) ch0 serial sound interface (ssi) ch0 ? interface (dsmif) ch0 to ch3 12-bit a/d converter (s12adc) an000 to an007 (unit 0) an100 to an115 (unit 1) an000 to an007 (unit 0) temperature sensor available crc calculator (crc) available data operation circuit (doc) available clock monitor circuit (clma) available secure boot mode* 1 optional event link controller (elc) available encoder interfaces* 2 optional
r01ds0228ej0060 rev.0.60 page 10 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 1.2 list of products table 1.3 is a list of products. table 1.3 list of products (1 / 2) part no. package cpu on-chip extended sram capacity ethercat operating frequency (max.) security function * 1 optional function r7s910001cfp 176 pins (plqp0176l d-a) cortex-r4f not supported not supported 450mhz not supported ? r7s910101cfp 176 pins (plqp0176l d-a) cortex-r4f not supported not supported 450mhz available ? r7s910002cbg 320 pins (prbg0320 ga-a) cortex-r4f not supported not supported 450mhz not supported ? r7s910102cbg 320 pins (prbg0320 ga-a) cortex-r4f not supported not supported 450mhz available ? r7s910006cbg 320 pins (prbg0320ga -a) cortex-r4f 1 mbyte not supported 450mhz not supported ? r7s910106cbg 320 pins (prbg0320ga -a) cortex-r4f 1 mbyte not supported 450mhz available ? r7s910007cbg 320 pins (prbg0320ga -a) cortex-r4f 1 mbyte not supported 600mhz not supported ? r7s910107cbg 320 pins (prbg0320ga -a) cortex-r4f 1 mbyte not supported 600mhz available ? r7s910011cbg 320 pins (prbg0320ga -a) cortex-r4f not supported not supported 450mhz not supported encoder i/f r7s910111cbg 320 pins (prbg0320ga -a) cortex-r4f not supported not supported 450mhz available encoder i/f r7s910013cbg 320 pins (prbg0320ga -a) cortex-r4f 1 mbyte not supported 600mhz not supported encoder i/f r7s910113cbg 320 pins (prbg0320ga -a) cortex-r4f 1 mbyte not supported 600mhz available encoder i/f r7s910015cbg 320 pins (prbg0320ga -a) cortex-r4f (1 mb for r- in engine) not supported 450mhz not supported r-in engine (cm3 : 150mhz) R7S910115CBG 320 pins (prbg0320ga -a) cortex-r4f (1 mb for r- in engine) not supported 450mhz available r-in engine (cm3 : 150mhz) r7s910016cbg 320 pins (prbg0320ga -a) cortex-r4f (1 mb for r- in engine) not supported 450mhz not supported r-in engine (cm3 : 150mhz) r7s910116cbg 320 pins (prbg0320ga -a) cortex-r4f (1 mb for r- in engine) not supported 450mhz available r-in engine (cm3 : 150mhz)
r01ds0228ej0060 rev.0.60 page 11 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. note: for the encoder i/f and r-in engine, see the relevant documents of each product. note 1. details of these optional functions will only be given after completion of a binding non-disclosure agreement. for detai ls, contact our sales representative. r7s910017cbg 320 pins (prbg0320ga -a) cortex-r4f (1 mb for r- in engine) not supported 600mhz not supported r-in engine (cm3 : 150mhz) r7s910117cbg 320 pins (prbg0320ga -a) cortex-r4f (1 mb for r- in engine) not supported 600mhz available r-in engine (cm3 : 150mhz) r7s910018cbg 320 pins (prbg0320ga -a) cortex-r4f (1 mb for r- in engine) not supported 600mhz not supported encoder i/f r-in engine (cm3 : 150mhz) r7s910118cbg 320 pins (prbg0320ga -a) cortex-r4f (1 mb for r- in engine) not supported 600mhz available encoder i/f r-in engine (cm3 : 150mhz) table 1.3 list of products (2 / 2) part no. package cpu on-chip extended sram capacity ethercat operating frequency (max.) security function * 1 optional function
r01ds0228ej0060 rev.0.60 page 12 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 1.3 block diagram figure 1.1 shows a block diagram of a 320-pin device. etherc: ethernet controller ecatc: ethercat slave contoller dmac: dma controller bsc: bus state controller spibsc: spi multi i/o bus controller wdta: watchdog timer iwdta: independent watchdog timer scifa: serial communication interface with fifo rspia: serial peripheral interface usb: usb 2.0 hs host/function module vic: vector interrupt controller nvic: nested-type vector interrupt controller mpu: memory protection unit elc: event link controller tpua: 16-bit timer pulse unit mtu3a: multi-function timer pulse unit 3 poe3: port output enable 3 gpta: general-purpose pwm timer ppg: programmable pulse generator cmt: compare match timer cmtw: compare match timer w riica: i 2 c bus interface rscan: can module ssi: serial sound interface dsmif: ? interface crc: crc (cyclic redundancy check) calculator clma: clock monitor circuit doc: data operation circuit ecm: error control module note 1. only included in products incorporating an r-in engine figure 1.1 block diagram cmt 2 channels (unit 1) cmtw 1 channel (unit 1) cmtw 1 channel (unit 0) cmt 2 channels (unit 2) bsc internal main bus 1 clock generation circuit cortex-r4f port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port a port b port c 12-bit a/d converter 16 channels (unit 1) mtu3a 9 channels wdta1ch products incorporating an r-in engine: wdta2ch riic 2 channels crc iwdta usb 1 port rscan 2 channels poe3 tpua 6 channels (unit 0) cmt 2 channels (unit 0) ppg (unit 1) ppg (unit 0) rspia 4 channels internal main bus 2 dmac 16 channels (unit 0) temperature sensor gpta 4 channels port d port e port f port g port h port j port k port l mpu scifa 5 channels etherc 3 ports ecatc *1 doc clma on-chip extended sram with ecc port p port m port n port t port r port s vic tcm internal peripheral buses 1 to 7 cortex-m3 *1 mpu nvic dmac 16 channels (unit 1) elc tpua 6 channels (unit 1) ssi dsmif 4 channels ecm 12-bit a/d converter 8 channels (unit 0) spibsc operand bus system bus instruction bus port u
r01ds0228ej0060 rev.0.60 page 13 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1 / 7) classifications pin name i/o description power supply vdd input power supply pin. connect this pin to the system power supply. vss input ground pin. connect this pin to the system power supply (0 v). vccq33 input power supply pin for i/o pins pllvdd0, pllvdd1 input power supply pins for the on-chip pll oscillator pllvss0, pllvss1 input ground pins for the on-chip pll oscillator. c onnect these pins to the system power supply (0 v). clock xtal output connected to a crystal re sonator. an external clock signal may also be input to the extal pin. extal input ckio output outputs the external bus clock for external devices. audio_clk input inputs the external clock for audio. clkout25m0, clkout25m1, clkout25m2 output output the external clock for ethernet phy. operating mode control md0 to md2 input input the operating mode select signal. system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low. bscanp input inputs the boundary scan enabl e signal. boundary scan is enabled when this pin goes high. when not used, it should be driven low. oscth input inputs the clock input mode select signal. when an external clock is input, this pin should be driven hi gh. when a crystal resonator is connected, it should be driven low. errorout# output outputs the error signal from the error control module (ecm). rstout# output outputs the reset signal externally. debugging interface trst# input on-chip emulator or boundary scan pins tms i/o tdi input tdo output tck input traceclk output outputs the clock for synchronization with the trace data. tracectl output outputs the enable signal for trace control. tracedata0 to 7 output output the trace data.
r01ds0228ej0060 rev.0.60 page 14 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. bus state controller (bsc) a0 to a25 output output the address. d0 to d31 i/o input and output the data. cs0# to cs5# output output the chip select signal for the external memory or device. rd# output outputs the strobe signal which indicates reading is in progress. rd/wr# output outputs the strobe signal which indicates the read or write access. bs# output outputs the status signal whic h indicates the start of bus cycles. ah# output outputs the address hold signal for the device that uses the multiplexed i/o bus. wait# input inputs the external wait control signal which inserts a wait cycle into the bus cycles. we0# output outputs the write strobe signal to d7 to d0. we1# output outputs the write strobe signal to d15 to d8. we2# output outputs the write strobe signal to d23 to d16. we3# output outputs the write strobe signal to d31 to d24. dqmll output outputs the data mask enable signal to d7 to d0 when sdram is connected. dqmlu output outputs the data mask enable signal to d15 to d8 when sdram is connected. dqmul output outputs the data mask enable signal to d23 to d16 when sdram is connected. dqmuu output outputs the data mask enable signal to d31 to d24 when sdram is connected. ras# output outputs the low-address strobe signal to the sdram. this pin should be connected to the ras pin on the sdram. cas# output outputs the column-address strobe signal to the sdram. this pin should be connected to the cas pin on the sdram. cke output outputs the clock enable signal to the sdram. this pin should be connected to the cke pin on the sdram. direct memory access controller (dmac) dreq0 to dreq2 input input the dma transfer request signal from the external device. dack0 to dack2 output output the acknowledge signal which indicates acceptance of the dma transfer request from the external device. tend0 to tend2 output output the dma transfer end signal. interrupt nmi input inputs the non-maskable interrupt request signal. irq0 to irq15 input input the external interrupt request signal. eth0_int, eth1_int, eth2_int input input the ethernet phy interrupt request signal. table 1.4 pin functions (2 / 7) classifications pin name i/o description
r01ds0228ej0060 rev.0.60 page 15 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. multi-function timer pulse unit 3 (mtu3a) mtioc0a, mtioc0b mtioc0c, mtioc0d i/o tgra0 to tgrd0 input capture input/output compare output/ pwm output pins mtioc1a, mtioc1b i/o tgra1 and tgrb1 input capture input/output compare output/ pwm output pins mtioc2a, mtioc2b i/o tgra2 and tgrb2 input capture input/output compare output/ pwm output pins mtioc3a, mtioc3b mtioc3c, mtioc3d i/o tgra3 to tgrd3 input capture input/output compare output/ pwm output pins mtioc4a, mtioc4b mtioc4c, mtioc4d i/o tgra4 to tgrd4 input capture input/output compare output/ pwm output pins mtic5u, mtic5v mtic5w input tgru5, tgrv5, and tgrw5 input capture input/dead time compensation input pins mtioc6a, mtioc6b mtioc6c, mtioc6d i/o tgra6 to tgrd6 input capture input/output compare output/ pwm output pins mtioc7a, mtioc7b mtioc7c, mtioc7d i/o tgra7 to tgrd7 input capture input/output compare output/ pwm output pins mtioc8a, mtioc8b mtioc8c, mtioc8d i/o tgra8 to tgrd8 input capture input/output compare output/ pwm output pins mtclka, mtclkb mtclkc, mtclkd input external clock input pins for mtu3a port output enable 3 (poe3) poe0#, poe4# poe8#, poe10# input input the request signal to place the mtu3a or gpta in the high impedance state. general-purpose pwm timer (gpta) gtioc0a, gtioc0b i/o gpt0.gtgra and gp t0.gtgrb input capture input/output compare output/pwm output pins gtioc1a, gtioc1b i/o gpt1.gtgra and gp t1.gtgrb input capture input/output compare output/pwm output pins gtioc2a, gtioc2b i/o gpt2.gtgra and gp t2.gtgrb input capture input/output compare output/pwm output pins gtioc3a, gtioc3b i/o gpt3.gtgra and gp t3.gtgrb input capture input/output compare output/pwm output pins gtetrg input external trigger input pin for gpt0 to gpt3 table 1.4 pin functions (3 / 7) classifications pin name i/o description
r01ds0228ej0060 rev.0.60 page 16 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 16-bit timer pulse unit (tpua) tioca0, tiocb0, tiocc0, tiocd0 i/o tpu0.tgra0 to tpu0.tgrd0 input capture input/output compare output/pwm output pins tioca1, tiocb1 i/o tpu0.tgra1 and tpu0.tgrb1 input capture input/output compare output/pwm output pins tioca2, tiocb2 i/o tpu0.tgra2 and tpu0.tgrb2 input capture input/output compare output/pwm output pins tioca3, tiocb3 tiocc3, tiocd3 i/o tpu0.tgra3 to tpu0.tgrd3 input capture input/output compare output/pwm output pins tioca4, tiocb4 i/o tpu0.tgra4 and tpu0.tgrb4 input capture input/output compare output/pwm output pins tioca5, tiocb5 i/o tpu0.tgra5 and tpu0.tgrb5 input capture input/output compare output/pwm output pins tclka, tclkb tclkc, tclkd input external clock input pins for tpu0 tioca6, tiocb6 tiocc6, tiocd6 i/o tpu1.tgra0 to tpu1.tgrd0 input capture input/output compare output/pwm output pins tioca7, tiocb7 i/o tpu1.tgra1 and tpu1.tgrb1 input capture input/output compare output/pwm output pins tioca8, tiocb8 i/o tpu1.tgra2 and tpu1.tgrb2 input capture input/output compare output/pwm output pins tioca9, tiocb9 tiocc9, tiocd9 i/o tpu1.tgra3 to tpu1.tgrd3 input capture input/output compare output/pwm output pins tioca10, tiocb10 i/o tpu1.tgra4 and tpu1.tgrb4 input capture input/output compare output/pwm output pins tioca11, tiocb11 i/o tpu1.tgra5 and tpu1.tgrb5 input capture input/output compare output/pwm output pins tclke, tclkf tclkg, tclkh input external clock input pins for tpu1 programmable pulse generator (ppg) po0 to po31 output pulse output pins compare match timer w (cmtw) tic0 to tic3 input cmtw input capture input pins toc0 to toc3 output cmtw output compare output pins serial communication interface with fifo (scifa) sck0 to sck4 i/o clock i/o pins rxd0 to rxd4 input input the receive data. txd0 to txd4 output output the transmit data. cts0# to cts4# input input pins for controlling the start of transmission and reception rts0# to rts4# output output pins for controlling the start of transmission and reception i 2 c bus interface (riica) scl0, scl1 i/o clock i/o pins. the bus can be directly driven by the n-channel open drain. sda0, sda1 i/o data i/o pins. the bus c an be directly driven by the n-channel open drain. table 1.4 pin functions (4 / 7) classifications pin name i/o description
r01ds0228ej0060 rev.0.60 page 17 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. ethernet controller (etherc) eth0_txc, eth1_txc, eth2_txc input input the 10 m/100 m transmission clock (2.5 mhz/25 mhz). eth0_txen, eth1_txen, eth2_txen output output the transmission enable signal. eth0_txer, eth1_txer, eth2_txer output output the transmission error signal. eth0_txd0 to 3, eth1_txd0 to 3, eth2_txd0 to 3 output output the transmission data signal. eth0_rxc, eth1_rxc, eth2_rxc i/o receive clock i/o pins eth0_rxdv, eth1_rxdv, eth2_rxdv input input the receive data enable signal. eth0_rxer, eth1_rxer, eth2_rxer input input the receive data error signal. eth0_rxd0 to 3, eth1_rxd0 to 3 input input the receive data signal. eth0_crs, eth1_crs, eth2_crs input input the carrier sense signal. eth0_col, eth1_col, eth2_col input input the collision detection signal. eth_mdc, mii2_mdc output output the management interface clock. eth_mdio, mii2_mdio i/o management data signal i/o pins phylink0, phylink1, phylink2 input input the phy link signal (for ether switch). ethswsecout output event output pin for ether switch per second phyresetout#, phyrestout2# output output the phy resetout signal. ethercat slave controller (ecatc) (only included in products incorporating an r-in engine) catledrun output outputs the ethercat run led signal. catirq output outputs the ethercat irq signal. catledster output outputs the ethercat dual-color state led signal. catlederr output outputs the ethercat error led signal. catlinkact0, catlinkact1 output output the ethercat link/activity led signal. catsync0, catsync1 output output the ethercat sync signal. catlatch0, catlatch1 input input the ethercat latch signal. cati2cclk output outputs the ethercat eeprom i 2 c clock signal. cati2cdata i/o inputs/outputs the ethercat eeprom i 2 c data signal. catrestout output outputs the ethercat phy resetout signal. table 1.4 pin functions (5 / 7) classifications pin name i/o description
r01ds0228ej0060 rev.0.60 page 18 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. usb 2.0 host/function module vdd33_usb input power supply input pin for usb vss_usb input ground input pin for usb dvdd_usb input digital power supply input pin for usb usb_rref input reference current input pin for usb. connect this pin to the avss33usb pin via 200 ? (1%). usb_dp i/o usb bus d+ data i/o pin usb_dm i/o usb bus d- data i/o pin usb_vbusen output outputs the vbus power enable signal for usb. usb_ovrcur input inputs the overcurrent signal for usb. usb_vbusin input usb cable connection/ disconnection detection input pin can module (rscan) crxd0 to crxd1 input receive data input pins ctxd0 to ctxd1 output transmit data output pins serial peripheral interface (rspia) rspck0 to rspck3 i/o clock i/o pins mosi0 to mosi3 i/o master transmit data i/o pins miso0 to miso3 i/o slave transmit data i/o pins ssl00, ssl10, ssl20, ssl30 i/o slave select signal i/o pins ssl01, ssl02, ssl03, ssl11 output slave select signal output pins spi multi i/o bus controller (spibsc) spbclk output clock output pin spbssl output slave select signal output pin spbmo/spbio0 i/o master transmit data/data 0 i/o pins spbmi/spbio1 i/o master input data/data 1 i/o pins spbio2 to 3 i/o data 2, data 3 i/o pins serial sound interface (ssi) ssisck0 i/o ssi serial bit clock i/o pin ssiws0 i/o word select i/o pin ssitxd0 output serial data output pin ssirxd0 input serial data input pin ? interface (dsmif) mclk0 to mclk3 i/o clock i/o pins mdat0 to mdat3 input data input pins 12-bit a/d converter (s12adc) an000 to an007, an100 to an115 input analog input pins for a/d converter adtrg0, adtrg1 input external trigger input pins for the start of a/d conversion an1_anex0 output extended analog outpu pin an1_anex1 input extended analog input pin analog power supply avcc0 input analog power supply in put pin for the 12-bit a/d converter (unit 0). connect this pin to the vccq33 pin if the 12-bit a/d converter is not to be used. avss0 input analog ground input pin for t he 12-bit a/d converter (unit 0). connect this pin to the vss pin if the 12-bit a/d converter is not to be used. vrefh0 input reference power supply input pin for the 12-bit a/d converter (unit 0). connect this pin to the vccq33 pin if the 12-bit a/d converter is not to be used. vrefl0 input reference ground pin for the 12-bit a/d converter (unit 0). connect this pin to the vss pin if the 12-bit a/d converter is not to be used. table 1.4 pin functions (6 / 7) classifications pin name i/o description
r01ds0228ej0060 rev.0.60 page 19 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. analog power supply avcc1 input analog power supply in put pin for the 12-bit a/d converter (unit 1). connect this pin to the vccq33 pin if the 12-bit a/d converter is not to be used. avss1 input analog ground input pin for the 12-bit a/d converter (unit 1). connect this pin to the vss pin if the 12-bit a/d converter is not to be used. vrefh1 input reference power supply input pin for the 12-bit a/d converter (unit 1). connect this pin to the vccq33 pin if the 12-bit a/d converter is not to be used. vrefl1 input reference ground pin for the 12-bit a/d converter (unit 1). connect this pin to the vss pin if the 12-bit a/d converter is not to be used. i/o ports p00 to p07 i/o 8-bit i/o pins p10 to p17 i/o 8-bit i/o pins p20 to p27 i/o 8-bit i/o pins p30 to p37 i/o 8-bit i/o pins p40 to p47 i/o 8-bit i/o pins p50 to p56 i/o 7-bit i/o pins p60 to p67 i/o 8-bit i/o pins p70 to p77 i/o 8-bit i/o pins p80 to p87 i/o 8-bit i/o pins p90 to p97 i/o 8-bit i/o pins pa0 to pa7 i/o 8-bit i/o pins pb0 to pb7 i/o 8-bit i/o pins pc0 to pc7 i/o 8-bit i/o pins pd0 to pd7 i/o 8-bit i/o pins pe0 to pe7 i/o 8-bit i/o pins pf5 to pf7 i/o 3-bit i/o pins pg0 to pg7 i/o 8-bit i/o pins ph0 to ph7 i/o 8-bit i/o pins pj0 to pj7 i/o 8-bit i/o pins pk0 to pk7 i/o 8-bit i/o pins pl0 to pl7 i/o 8-bit i/o pins pm0 to pm7 i/o 8-bit i/o pins pn0 to pn7 i/o 8-bit i/o pins pp0 to pp7 i/o 8-bit i/o pins pr0 to pr7 i/o 8-bit i/o pins ps0 to ps7 i/o 8-bit i/o pins pt0 to pt7 i/o 8-bit i/o pins pu0 to pu7 i/o 8-bit i/o pins table 1.4 pin functions (7 / 7) classifications pin name i/o description
r01ds0228ej0060 rev.0.60 page 20 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 1.5 pin assignments figure 1.2 and figure 1.3 show the pin arrangement. table 1.5 and table 1.6 show the pin assignments. table 1.7 and table 1.8 show the lists of pin functions. figure 1.2 pin arrangement (320-pin fbga) 1234567891011121314151617181920 a vss pc2 pj3 pj1 pf7 pb4 pb0 pc0 pf6 vcc q33 b p54 vss an0 07 an0 05 an0 02 avc c0 avc c1 vre fh1 p17 vss a b pj5 pj4 pc3 pj2 pj0 pb5 pb2 pc1 pb7 p86 pd7 p52 an0 06 an0 03 an0 01 avs s0 avs s1 vre fl1 p16 p15 b c pj7 pj6 pu2 pl7 pl5 pb6 pb3 pb1 pf5 p87 pd6 p53 p51 an0 04 an0 00 vre fl0 vre fh0 pd2 p14 p13 c dp81 p80 pu3 pd0 p96 p95 d e p84 p82 pu1 pu0 pl6 pl4 pl2 pl0 pk7 pk6 pd5 p56 pd4 vcc q33 pd1 p97 p94 p93 e f pc4 p83 p85 pu4 vss vcc q33 pl3 pl1 pk5 pk4 p55 p50 pd3 pk2 p90 p92 p91 p12 f gpu6 pc5 vcc q33 pu5 pm0 pk3 pa7 pa4 pa3 p11 g hpu7 pm1 p35 err oro ut vcc q33 vdd vdd vdd vdd vdd vss pa6 pa5 pa2 pk0 pk1 h jpm6 pm3 pm2 p33 trs t# vdd vss vss vss vss vdd vcc q33 pa1 pa0 pt7 pt6 j kpm7 pm5 pm4 p34 pll vdd 1 vdd vss vss vss vss vdd vss p77 p76 p75 pt5 k l md1 md2 tms tck pll vss 1 vdd vss vss vss vss vdd vss pe7 p72 p73 p74 l mxta l ext al osc th bsc anp pll vdd 0 vdd vss vss vss vss vdd vcc q33 pe6 p70 pt4 p71 m n vss md0 rst out # res # pll vss 0 vdd vss vdd vdd vdd vdd pe2 pe4 pe5 pt2 pt3 n pvss _us b vdd 33_ usb usb _rr ef p31 vcc q33 p06 p07 pe3 pt0 pt1 p rusb _dp usb _dm p 30 pn0 pn2 pg0 pg2 pg7 ph2 ph4 ph6 p23 p27 p47 vcc q33 vcc q33 ps6 ps7 r tdvd d_u sb vdd 33_ usb p32 pc6 p37 p36 pg3 pg6 ph3 vcc q33 ph5 vcc q33 p26 vcc q33 vss vss pe0 pe1 t up60 p63 pn1 p00 p04 p03 u v p61 p64 pn3 pn4 pc7 pg1 pg4 pg5 ph0 ph1 ph7 p20 p21 vss p45 p46 ps2 p05 p01 p02 v w p62 p65 pn5 pn6 pp0 pp2 pp4 pp6 pp7 pr1 pr3 pr5 p24 p22 p44 p43 ps1 ps3 ps4 ps5 w y vss p67 p66 pn7 pp1 pp3 pp5 vss pr0 pr2 pr4 pr6 pr7 p25 p41 p42 p40 ps0 p10 vss y 1234567891011121314151617181920
r01ds0228ej0060 rev.0.60 page 21 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. note: this figure indicates the power supply pins and i/o port pins. for t he pin configuration, see table 1.8, list of pin and p in functions (176-pin hlqfp). figure 1.3 pin arrangement (176-pin hlqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 vccq33 vrefh0 vrefl0 avss0 avcc0 an000 an001 an002 an003 an004 an005 an006 vdd vss p51 p54 p56 vccq33 pd5 pd6 pd7 p86 p87 pf5 pb7 vss pc1 pb1 pb3 pb5 vss pc2 p17 an007 vccq33 vss p15 p13 vdd vss pa7 vccq33 pa6 pa5 pa4 pa3 pa2 vdd vss pa0 p77 p76 p75 p74 p73 p72 p71 p70 vdd vss pe7 pe5 pe4 vss pe1 p07 p05 p04 p00 p14 pa1 p01 pc3 vss vdd p82 p85 errorout p35 trst# p33 vss vdd p34 tms bscanp oscth md0 vccq33 extal xtal md1 pllvdd0 vss usb_vbus0 usb_dp usb_rref usb_xi p60 p61 p62 vss vccq33 tck res# p16 md2 pllvss0 rstout# usb_dm usb_xo p30 vccq33 p63 p64 p65 vccq33 vss vdd p36 p37 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 ph0 ph2 ph3 p22 p20 p25 p26 p27 vdd vss p42 p40 p43 ph1 vdd vss ph4 ph5 ph6 ph7 p24 p21 p23 p47 vccq33 p10 vss pe6 pe3 pe2 pe0 p06 vccq33 esd_vdd p03 pf6 vdd pc0 pb0 pb2 pb4 vdd pb6 rz/t group (176-pin hlqfp) (top view) pllvdd1 pllvss1 vdd usb_id0
r01ds0228ej0060 rev.0.60 page 22 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. table 1.5 pin assignments (320-pin fbga) (1 / 8) pin number pin name a1 vss a2 pc2 / eth0_txc / eth1_rxd2 / cati2cdata / sda0 a3 pj3 / irq11 / eth0_txd0 / adtrg0 a4 pj1 / eth0_txd2 / catledster / rspck3 a5 pf7 / irq7 / a25 / eth0_txer / rts3# / ssl30 a6 pb4 / a24 / eth1_col / eth0_rxer / catsync0 / catlatch0 / rxd3 / mosi3_blue / mdat0 a7 pb0 / eth1_rxdv / mtclkb / tclkd / tic3 a8 pc0 / wait# / eth1_rxd2 / gtetrg / scl1 / mdat3 a9 pf6 / eth1_rxd0 / mtioc3d / gtioc0b / toc2 a10 vccq33 a11 p54 / clkout25m1 / mosi2_red a12 vss a13 an007 a14 an005 a15 an002 a16 avcc0 a17 avcc1 a18 vrefh1 a19 p17 / cs5# / eth1_txer / phyresetout# / adtrg0 a20 vss b1 pj5 / eth0_rxd1 / tiocd0 / rxd3 b2 pj4 / eth0_rxd0 / txd3 b3 pc3 / eth0_rxc / eth0_rxdv / cati2cclk / rxd4 / scl0 / crxd1 b4 pj2 / irq10 / eth0_txd1 / miso3 b5 pj0 / irq8 / eth0_txd3 / catlederr / mosi3_red b6 pb5 / eth_mdio / tclkb / poe0# / poe10# / cts3# / rspck3 b7 pb2 / eth1_rxc / eth0_rxd1 / catsync1 / catlatch1 / mtioc1a / ssl30 / mdat1 b8 pc1 / irq9 / eth1_rxd3 / phylink0 / sda1 / mdat2 b9 pb7 / eth1_rxd1 / mtioc3b / gtioc0a / toc3 b10 p86 / an1_anex0 / eth1_txd0 / mtioc4b / gtioc2a / toc1 / rspck2 b11 pd7 / an115 / eth1_txd1 / mtioc4d / gtioc2b / toc0 b12 p52 / eth0_int / ssl20 b13 an006 b14 an003 b15 an001 b16 avss0 b17 avss1 b18 vrefl1 b19 p16 / cs4# / cs2# / mtioc3b / gtioc0a b20 p15 / cs3# / cke / mtioc3d / gtioc0b c1 pj7 / irq15 / eth0_rxd3 / catledrun / cts3# c2 pj6 / irq14 / eth0_rxd2 / catirq / sck3 c3 pu2 / irq2 / eth2_crs / tiocd9 / rxd3 c4 pl7 / irq15 / eth2_rxdv
r01ds0228ej0060 rev.0.60 page 23 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. c5 pl5 / eth2_rxd2 / tioca8 c6 pb6 / eth_mdc / tclka / sck3 / rts4# / miso3 c7 pb3 / irq3 / cs1# / eth1_crs / phyresetout# / txd3 / ctxd1 / mclk0 c8 pb1 / eth1_rxer / mtclka / tclkc / cts4# c9 pf5 / eth1_txen / mtioc4a / gtioc1a / tic2 c10 p87 / an1_anex1 / a23 / eth1_txc / eth0_rxd0 / mtioc4c / gtioc1b / mclk1 c11 pd6 / an114 / a22 / eth1_txd2 / eth0_txd1 / tic1 / miso2 / mclk2 c12 p53 / eth1_int / miso2 c13 p51 / irq1 / phylink1 / rspck2 c14 an004 c15 an000 c16 vrefl0 c17 vrefh0 c18 pd2 / an110 / wait# c19 p14 / cas# / mtioc4a / gtioc1a c20 p13 / ras# / mtioc4c / gtioc1b d1 p81 / eth0_rxer / tiocc0 / cts4# d2 p80 / irq8 / eth0_rxdv / tiocc3 / rts4# d3 pu3 / eth2_col / tiocd6 / txd3 d18 pd0 / an108 / cs4# d19 p96 / an106 / poe0# / poe10# d20 p95 / an105 / irq13 / mtclka / cts2# e1 p84 / eth0_col / catlinkact1 / rxd4 e2 p82 / eth0_txen / eth1_crs / tiocd3 / sck4 / rts3# / usb_ovrcur e3 pu1 / eth2_rxc / tioca11 / sck3 e5 pu0 / eth2_rxer / tioca10 e6 pl6 / eth2_rxd3 / tioca9 e7 pl4 / irq4 / eth2_rxd1 e8 pl2 / eth2_txen / tioca6 / adtrg1 e9 pl0 / eth2_txd0 / tiocb9 e10 pk7 / eth2_txd2 / tiocb7 e11 pk6 / eth2_txd3 / tiocb6 e12 pd5 / an113 / a21 / eth1_txd3 / eth0_txd0 / tic0 / ssl20 / mclk3 e13 p56 / bs# / eth1_txer e14 pd4 / an112 / eth2_int e15 vccq33 e16 pd1 / an109 / cs1# e18 p97 / an107 / irq7 / a25 / adtrg1 e19 p94 / an104 / irq4 / mtclkb / rts2# e20 p93 / an103 / mtioc1a / tic3 / sck2 f1 pc4 / cati2cclk / tclkh / scl0 f2 p83 / irq11 / eth0_crs / catlinkact0 / txd4 f3 p85 / irq5 / clkout25m0 / txd4 / sck4 / usb_vbusen f5 pu4 / mii2_mdc / tiocc9 / cts3# f6 vss table 1.5 pin assignments (320-pin fbga) (2 / 8) pin number pin name
r01ds0228ej0060 rev.0.60 page 24 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. f7 vccq33 f8 pl3 / eth2_rxd0 / tioca7 f9 pl1 / eth2_txc / tiocb10 f10 pk5 / eth2_txd1 / tiocb8 f11 pk4 / eth2_txer / tiocb11 / mosi2_blue f12 p55 / irq5 / a24 / ethswsecout f13 p50 / irq8 / cs1# / phylink0 f14 pd3 / an111 / phyresetout2# f15 pk2 / a23 f16 p90 / an100 / ras# / tioca5 / txd4 f18 p92 / an102 / cs5# / toc3 / rxd2 f19 p91 / an101 / cas# / txd2 f20 p12 / mtioc4b / gtioc2a g1 pu6 / phyresetout# / tclkf / cts4# g2 pc5 / cati2cdata / tclkg / sda0 g3 vccq33 g5 pu5 / irq13 / mii2_mdio / tiocc6 / rts3# g6 pm0 / clkout25m2 / txd4 g15 pk3 / a24 g16 pa7 / irq7 / d31 / a22 / mtioc6b / gtioc3b / rts2# / mclk0 g18 pa4 / d28 / eth1_int / tioca3 / adtrg0 / rxd2 / tend2 / mdat1 g19 pa3 / d27 / ethswsecout / gtetrg / tioca2 / sck2 / dack2 / mclk2 g20 p11 / irq9 / mtioc4d / gtioc2b h1 pu7 / catirq / rxd4 h2 pm1 / catlederr / sck4 h3 p35 / nmi h5 errorout h6 vccq33 h8 vdd h9 vdd h10 vdd h11 vdd h12 vdd h13 vss h15 pa6 / irq6 / d30 / a21 / gtioc3a / cts2# / mdat0 h16 pa5 / d29 / eth0_int / eth1_txer / tioca4 / txd2 / mclk1 h18 pa2 / d26 / mtioc3b / gtioc0a / ssl02 / dreq2 h19 pk0 / cas# / po31 h20 pk1 / cs5# j1 pm6 / irq6 / catlinkact0 / po19 j2 pm3 / catsync0 / catlatch0 / po16 j3 pm2 / catsync1 / catlatch1 / tclke / rts4# j5 p33 / tdo j6 trst# j8 vdd table 1.5 pin assignments (320-pin fbga) (3 / 8) pin number pin name
r01ds0228ej0060 rev.0.60 page 25 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. j9 vss j10 vss j11 vss j12 vss j13 vdd j15 vccq33 j16 pa1 / d25 / mtioc3d / gtioc0b / miso0 / audio_clk / tracedata7 / mclk3 j18 pa0 / d24 / mtioc4a / gtioc1a / mosi0_red / tracedata6 / mdat3 j19 pt7 / a22 / dack2 j20 pt6 / a21 / dreq2 k1 pm7 / catlinkact1 / po20 k2 pm5 / catledster / po18 k3 pm4 / catledrun / po17 k5 p34 / tdi k6 pllvdd1 k8 vdd k9 vss k10 vss k11 vss k12 vss k13 vdd k15 vss k16 p77 / d23 / mtioc4c / gtioc1b / rspck0 / tracedata5 k18 p76 / d22 / mtioc4b / gtioc2a / ssl01 / ssiws0 / tracedata4 k19 p75 / irq13 / d21 / mtioc4d / gtioc2b / ssl00 / tracedata3 k20 pt5 / bs# / po30 / tend2 l1 md1 l2 md2 l3 tms l5 tck l6 pllvss1 l8 vdd l9 vss l10 vss l11 vss l12 vss l13 vdd l15 vss l16 pe7 / d15 / mtioc7a / tiocd3 / poe8# / sck1 / rspck0 / tracedata7 l18 p72 / d18 / mtioc1a / tic2 / txd1 / ssitxd0 / tracedata0 l19 p73 / irq3 / d19 / mtclkb / rxd1 / ssirxd0 / tracedata1 l20 p74 / d20 / mtclka / cts1# / ssl03 / ssisck0 / tracedata2 m1 xtal m2 extal m3 oscth table 1.5 pin assignments (320-pin fbga) (4 / 8) pin number pin name
r01ds0228ej0060 rev.0.60 page 26 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. m5 bscanp m6 pllvdd0 m8 vdd m9 vss m10 vss m11 vss m12 vss m13 vdd m15 vccq33 m16 pe6 / irq6 / d14 / mtioc0a / tiocd0 / rxd1 / miso0 / tracedata6 m18 p70 / irq0 / d16 / mtioc6d / rts1# / usb_ovrcur / traceclk m19 pt4 / cs3# / po29 m20 p71 / d17 / d7 / poe0# / poe10# / toc2 / sck1 / tracectl n1 vss n2 md0 n3 rstout# n5 res# n6 pllvss0 n8 vdd n9 vss n10 vdd n11 vdd n12 vdd n13 vdd n15 pe2 / irq2 / d10 / mtclkc / tiocb4 / ssl02 / tracedata2 n16 pe4 / d12 / mtioc0b / tiocc0 / rts1# / ssl00 / tracedata4 n18 pe5 / d13 / mtioc0c / tiocc3 / txd1 / mosi0_blue / tracedata5 n19 pt2 / tioca1 / tiocb1 / po27 n20 pt3 / irq11 / tioca0 / tiocb0 / po28 / cts2# p1 vss_usb p2 vdd33_usb p3 usb_rref p5 p31 / usb_vbusen p6 vccq33 p15 p06 / d6 / mtioc2b / tiocb0 p16 p07 / d7 / mtioc2a / tiocb1 p18 pe3 / irq3 / d11 / mtioc0d / tiocb5 / cts1# / ssl01 / tracedata3 p19 pt0 / irq0 / refout# / irqout# / tioca3 / tiocb3 / po25 / sck2 p20 pt1 / tioca2 / tiocb2 / po26 / rts2# r1 usb_dp r2 usb_dm r3 p30 / crxd0 / usb_vbusin r5 pn0 / mtioc8d / ssl10 r6 pn2 / irq10 / mtioc8b / mosi1_blue r7 pg0 / a1 / po2 table 1.5 pin assignments (320-pin fbga) (5 / 8) pin number pin name
r01ds0228ej0060 rev.0.60 page 27 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. r8 pg2 / a3 / we0#/dqmll / po4 / toc0 / rspck1 r9 pg7 / a8 / po9 r10 ph2 / a11 / mtioc2a / po12 r11 ph4 / irq4 / a13 / po14 r12 ph6 / a15 / mtioc7d / rts0# r13 p23 / a0 / mtic5u / txd0 / dack1 r14 p27 / a20 / d4 / mtioc8c / tiocb0 / rts0# r15 p47 / we3#/dqmuu/ah# / mtioc6c r16 vccq33 r18 vccq33 r19 ps6 / irq14 / breq# / tioca5 / tiocb5 / po23 / rxd2 r20 ps7 / back# / tioca4 / tiocb4 / po24 / txd2 t1 dvdd_usb t2 vdd33_usb t3 p32 / irq10 / usb_ovrcur t5 pc6 / tclkc / scl1 / crxd0 / dreq0 / usb_vbusin t6 p37 / we1#/dqmlu / po1 t7 p36 / we0#/dqmll / po0 t8 pg3 / a4 / a1 / po5 / tic1 / miso1 t9 pg6 / a7 / d3 / tclkb / po8 / ssl11 t10 ph3 / a12 / mtioc1b / po13 t11 vccq33 t12 ph5 / a14 / po15 t13 vccq33 t14 p26 / a19 / mtioc8d / dreq1 t15 vccq33 t16 vss t18 vss t19 pe0 / d8 / mtioc1b / tiocb2 / tracedata0 t20 pe1 / d9 / mtclkd / tiocb3 / ssl03 / tracedata1 u1 p60 / spbssl / ctxd0 / tend0 u2 p63 / spbmo/spbio0 u3 pn1 / mtioc8c / po21 / miso1 u18 p00 / d0 / mtioc6a / tioca1 / adtrg1 / tracectl u19 p04 / d4 / mtioc3c / tioca5 u20 p03 / d3 / mtic5u / tioca4 v1 p61 / spbio3 / ctxd1 / dack0 v2 p64 / spbmi/spbio1 v3 pn3 / mtioc8a / rspck1 v4 pn4 / irq12 / mtioc6c / tiocc6 / ssl11 v5 pc7 / tic0 / sda1 / crxd1 v6 pg1 / a2 / po3 v7 pg4 / a5 / d1 / po6 / toc1 / mosi1_red v8 pg5 / a6 / d2 / tclka / po7 / ssl10 v9 ph0 / a9 / po10 table 1.5 pin assignments (320-pin fbga) (6 / 8) pin number pin name
r01ds0228ej0060 rev.0.60 page 28 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. v10 ph1 / a10 / mtioc2b / po11 v11 ph7 / a16 / mtic5w v12 p20 / a17 / mtclkd v13 p21 / irq1 / cs0# / mtic5v / tiocb1 / cts0# v14 vss v15 p45 / cs2# v16 p46 / cke v17 ps2 / mtioc7c / ssiws0 v18 p05 / d5 / mtioc3a v19 p01 / d1 / mtic5w / tioca2 v20 p02 / d2 / mtic5v / tioca3 w1 p62 / spbclk w2 p65 / spbio2 / dreq0 w3 pn5 / irq5 / mtioc6a / tiocd9 w4 pn6 / mtioc3c / tiocc9 / mclk3 w5 pp0 / poe8# / tend0 / mclk2 w6 pp2 / mtioc0c / tclkh / mclk1 w7 pp4 / mtioc0a / mclk0 w8 pp6 / tioca11 / rxd1 / tracectl w9 pp7 / tclkf / tclkh / sck1 / dack1 / traceclk w10 pr1 / irq9 / poe4# / cts1# / tend1 / tracedata1 w11 pr3 / tioca10 / tiocb10 / tracedata3 w12 pr5 / tioca8 / tiocb8 / tracedata5 w13 p24 / irq12 / rd/wr# / rxd0 w14 p22 / irq2 / rd# / mtioc7b / tiocd0 / sck0 w15 p44 / irq12 / wait# / tclkd / adtrg0 / cts0# w16 p43 / we2#/dqmul / mtioc8b / usb_vbusen w17 ps1 / irq1 / mtioc7b / ssisck0 w18 ps3 / mtioc7a / ssirxd0 w19 ps4 / mtioc6d / ssitxd0 w20 ps5 / mtioc6b y1 vss y2 p67 / irq15 / gtioc3b / ctxd0 / tend0 / usb_ovrcur y3 p66 / irq14 / gtioc3a / ctxd1 / dack0 / usb_vbusen y4 pn7 / mtioc3a / tiocd6 / dreq0 / mdat3 y5 pp1 / mtioc0d / dack0 / mdat2 y6 pp3 / mtioc0b / tclkc / mdat1 y7 pp5 / po22 / mdat0 y8 vss y9 pr0 / tclke / tclkg / txd1 / dreq1 / tracedata0 y10 pr2 / tioca11 / tiocb11 / rts1# / tracedata2 y11 pr4 / tioca9 / tiocb9 / tracedata4 y12 pr6 / tioca7 / tiocb7 / tracedata6 y13 pr7 / tioca6 / tiocb6 / tracedata7 y14 p25 / a18 / mtclkc / tend1 table 1.5 pin assignments (320-pin fbga) (7 / 8) pin number pin name
r01ds0228ej0060 rev.0.60 page 29 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. y15 p41 / bs# / sck0 y16 p42 / d5 / mtioc7c / rxd0 y17 p40 / d6 / mtioc8a / txd0 y18 ps0 / mtioc7d / audio_clk y19 p10 / irq0 / ckio / tioca0 / traceclk y20 vss table 1.5 pin assignments (320-pin fbga) (8 / 8) pin number pin name
r01ds0228ej0060 rev.0.60 page 30 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. table 1.6 pin assignments (176-pin hlqfp) (1 / 4) pin number pin name 1 pc3 / eth0_rxc / eth0_rxdv / cati2cclk / rxd4 / scl0 / crxd1 2 vccq33 3vss 4vdd 5 p82 / eth0_txen / eth1_crs / tiocd3 / sck4 / rts3# / usb_ovrcur 6 p85 / irq5 / clkout25m0 / txd4 / sck4 / usb_vbusen 7 errorout 8 p35 / nmi 9trst# 10 p33 / tdo 11 p34 / tdi 12 tms 13 tck 14 bscanp 15 vdd 16 vss 17 md2 18 md1 19 pllvdd1 20 pllvss1 21 oscth 22 vccq33 23 extal 24 xtal 25 vss 26 md0 27 pllvdd0 28 pllvss0 29 res# 30 rstout# 31 vdd 32 vss 33 usb_id0 34 usb_vbus0 35 usb_dp 36 usb_dm 37 usb_rref 38 usb_xo 39 usb_xi 40 p30 / crxd0 / usb_vbusin 41 p60 / spbssl / ctxd0 / tend0 42 p61 / spbio3 / ctxd1 / dack0 43 vccq33 44 p62 / spbclk
r01ds0228ej0060 rev.0.60 page 31 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 45 vss 46 p63 / spbmo/spbio0 47 p64 / spbmi/spbio1 48 p65 / spbio2 / dreq0 49 vss 50 vdd 51 p36 / we0#/dqmll / po0 52 p37 / we1#/dqmlu / po1 53 pg0 / a1 / po2 54 pg1 / a2 / po3 55 vccq33 56 pg2 / a3 / we0#/dqmll / po4 / toc0 / rspck1 57 pg3 / a4 / a1 / po5 / tic1 / miso1 58 pg4 / a5 / d1 / po6 / toc1 / mosi1_red 59 pg5 / a6 / d2 / tclka / po7 / ssl10 60 pg6 / a7 / d3 / tclkb / po8 / ssl11 61 pg7 / a8 / po9 62 ph0 / a9 / po10 63 ph1 / a10 / mtioc2b / po11 64 ph2 / a11 / mtioc2a / po12 65 ph3 / a12 / mtioc1b / po13 66 vdd 67 vss 68 ph4 / irq4 / a13 / po14 69 ph5 / a14 / po15 70 ph6 / a15 / mtioc7d / rts0# 71 ph7 / a16 / mtic5w 72 p24 / irq12 / rd/wr# / rxd0 73 p21 / irq1 / cs0# / mtic5v / tiocb1 / cts0# 74 p22 / irq2 / rd# / mtioc7b / tiocd0 / sck0 75 p23 / a0 / mtic5u / txd0 / dack1 76 p20 / a17 / mtclkd 77 p25 / a18 / mtclkc / tend1 78 p26 / a19 / mtioc8d / dreq1 79 p27 / a20 / d4 / mtioc8c / tiocb0 / rts0# 80 vdd 81 vss 82 p42 / d5 / mtioc7c / rxd0 83 p40 / d6 / mtioc8a / txd0 84 p43 / we2#/dqmul / mtioc8b / usb_vbusen 85 p47 / we3#/dqmuu/ah# / mtioc6c 86 vccq33 87 p10 / irq0 / ckio / tioca0 / traceclk 88 vss 89 p00 / d0 / mtioc6a / tioca1 / adtrg1 / tracectl table 1.6 pin assignments (176-pin hlqfp) (2 / 4) pin number pin name
r01ds0228ej0060 rev.0.60 page 32 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 90 p01 / d1 / mtic5w / tioca2 91 esd_vdd 92 vccq33 93 p03 / d3 / mtic5u / tioca4 94 p04 / d4 / mtioc3c / tioca5 95 p05 / d5 / mtioc3a 96 p06 / d6 / mtioc2b / tiocb0 97 p07 / d7 / mtioc2a / tiocb1 98 pe0 / d8 / mtioc1b / tiocb2 / tracedata0 99 pe1 / d9 / mtclkd / tiocb3 / ssl03 / tracedata1 100 vss 101 pe2 / irq2 / d10 / mtclkc / tiocb4 / ssl02 / tracedata2 102 pe3 / irq3 / d11 / mtioc0d / tiocb5 / cts1# / ssl01 / tracedata3 103 pe4 / d12 / mtioc0b / tiocc0 / rts1# / ssl00 / tracedata4 104 pe5 / d13 / mtioc0c / tiocc3 / txd1 / mosi0_blue / tracedata5 105 pe6 / irq6 / d14 / mtioc0a / tiocd0 / rxd1 / miso0 / tracedata6 106 pe7 / d15 / mtioc7a / tiocd3 / poe8# / sck1 / rspck0 / tracedata7 107 vss 108 vdd 109 p70 / irq0 / d16 / mtioc6d / rts1# / usb_ovrcur / traceclk 110 p71 / d17 / d7 / poe0# / poe10# / toc2 / sck1 / tracectl 111 p72 / d18 / mtioc1a / tic2 / txd1 / ssitxd0 / tracedata0 112 p73 / irq3 / d19 / mtclkb / rxd1 / ssirxd0 / tracedata1 113 p74 / d20 / mtclka / cts1# / ssl03 / ssisck0 / tracedata2 114 p75 / irq13 / d21 / mtioc4d / gtioc2b / ssl00 / tracedata3 115 p76 / d22 / mtioc4b / gtioc2a / ssl01 / ssiws0 / tracedata4 116 p77 / d23 / mtioc4c / gtioc1b / rspck0 / tracedata5 117 pa0 / d24 / mtioc4a / gtioc1a / mosi0_red / tracedata6 / mdat3 118 pa1 / d25 / mtioc3d / gtioc0b / miso0 / audio_clk / tracedata7 / mclk3 119 vss 120 vdd 121 pa2 / d26 / mtioc3b / gtioc0a / ssl02 / dreq2 122 pa3 / d27 / ethswsecout / gtetrg / tioca2 / sck2 / dack2 / mclk2 123 pa4 / d28 / eth1_int / tioca3 / adtrg0 / rxd2 / tend2 / mdat1 124 pa5 / d29 / eth0_int / eth1_txer / tioca4 / txd2 / mclk1 125 pa6 / irq6 / d30 / a21 / gtioc3a / cts2# / mdat0 126 vccq33 127 pa7 / irq7 / d31 / a22 / mtioc6b / gtioc3b / rts2# / mclk0 128 vdd 129 vss 130 p13 / ras# / mtioc4c / gtioc1b 131 p14 / cas# / mtioc4a / gtioc1a 132 p15 / cs3# / cke / mtioc3d / gtioc0b 133 p16 / cs4# / cs2# / mtioc3b / gtioc0a 134 p17 / cs5# / eth1_txer / phyresetout# / adtrg0 table 1.6 pin assignments (176-pin hlqfp) (3 / 4) pin number pin name
r01ds0228ej0060 rev.0.60 page 33 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 135 vccq33 136 avcc1 137 vrefl0 138 avss0 139 avcc0 140 an000 141 an001 142 an002 143 an003 144 an004 145 an005 146 an006 147 an007 148 vdd 149 vss 150 p51 / irq1 / phylink1 / rspck2 151 p54 / clkout25m1 / mosi2_red 152 p56 / bs# / eth1_txer 153 pd5 / an113 / a21 / eth1_txd3 / eth0_txd0 / tic0 / ssl20 / mclk3 154 pd6 / an114 / a22 / eth1_txd2 / eth0_txd1 / tic1 / miso2 / mclk2 155 pd7 / an115 / eth1_txd1 / mtioc4d / gtioc2b / toc0 156 p86 / an1_anex0 / eth1_txd0 / mtioc4b / gtioc2a / toc1 / rspck2 157 p87 / an1_anex1 / a23 / eth1_txc / eth0_rxd0 / mtioc4c / gtioc1b / mclk1 158 pf5 / eth1_txen / mtioc4a / gtioc1a / tic2 159 vccq33 160 vdd 161 vss 162 pf6 / eth1_rxd0 / mtioc3d / gtioc0b / toc2 163 pb7 / eth1_rxd1 / mtioc3b / gtioc0a / toc3 164 pc0 / wait# / eth1_rxd2 / gtetrg / scl1 / mdat3 165 pc1 / irq9 / eth1_rxd3 / phylink0 / sda1 / mdat2 166 pb0 / eth1_rxdv / mtclkb / tclkd / tic3 167 pb1 / eth1_rxer / mtclka / tclkc / cts4# 168 pb2 / eth1_rxc / eth0_rxd1 / catsync1 / catlatch1 / mtioc1a / ssl30 / mdat1 169 vccq33 170 pb3 / irq3 / cs1# / eth1_crs / phyresetout# / txd3 / ctxd1 / mclk0 171 pb4 / a24 / eth1_col / eth0_rxer / catsync0 / catlatch0 / rxd3 / mosi3_blue / mdat0 172 pb5 / eth_mdio / tclkb / poe0# / poe10# / cts3# / rspck3 173 vss 174 vdd 175 pb6 / eth_mdc / tclka / sck3 / rts4# / miso3 176 pc2 / eth0_txc / eth1_rxd2 / cati2cdata / sda0 table 1.6 pin assignments (176-pin hlqfp) (4 / 4) pin number pin name
r01ds0228ej0060 rev.0.60 page 34 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. table 1.7 list of pin and pin functions (320-pin fbga) (1 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif) a1 vss a2 pc2 eth0_txc / eth1_rxd2 / cati2cdata / sda0 a3 pj3 eth0_txd0 irq11 adtrg0 a4 pj1 eth0_txd2 / catledster / rspck3 a5 pf7 a25 eth0_txer / rts3# / ssl30 irq7 a6 pb4 a24 eth1_col / eth0_rxer / catsync0 / catlatch0 / rxd3 / mosi3_blue mdat0 a7 pb0 mtclkb / tclkd / tic3 eth1_rxdv a8 pc0 wait# gtetrg eth1_rxd2 / scl1 mdat3 a9 pf6 mtioc3d / gtioc0b / toc2 eth1_rxd0 a10 vccq33 a11 p54 clkout25m1 / mosi2_red a13 an007 a14 an005 a15 an002 a16 avcc0 a17 avcc1 a18 vrefh1 a19 p17 cs5# eth1_txer / phyresetout# adtrg0 a20 vss b1 pj5 tiocd0 eth0_rxd1 / rxd3 b2 pj4 eth0_rxd0 / txd3 b3 pc3 eth0_rxc / eth0_rxdv / cati2cclk / rxd4 / scl0 / crxd1 b4 pj2 eth0_txd1 / miso3 irq10 b5 pj0 eth0_txd3 / catlederr / mosi3_red irq8 b6 pb5 tclkb / poe0# / poe10# eth_mdio / cts3# / rspck3
r01ds0228ej0060 rev.0.60 page 35 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. b7 pb2 mtioc1a eth1_rxc / eth0_rxd1 / catsync1 / catlatch1 / ssl30 mdat1 b8 pc1 eth1_rxd3 / phylink0 / sda1 mdat2 irq9 b9 pb7 mtioc3b / gtioc0a / toc3 eth1_rxd1 b10 p86 mtioc4b / gtioc2a / toc1 eth1_txd0 / rspck2 an1_ane x0 b11 pd7 mtioc4d / gtioc2b / toc0 eth1_txd1 an115 b12 p52 eth0_int / ssl20 b13 an006 b14 an003 b15 an001 b16 avss0 b17 avss1 b18 vrefl1 b19 p16 cs4# / cs2# mtioc3b / gtioc0a b20 p15 cs3# / cke mtioc3d / gtioc0b c1 pj7 eth0_rxd3 / catledrun / cts3# irq15 c2 pj6 eth0_rxd2 / catirq / sck3 irq14 c3 pu2 tiocd9 eth2_crs / rxd3 irq2 c4 pl7 eth2_rxdv irq15 c5 pl5 tioca8 eth2_rxd2 c6 pb6 tclka eth_mdc / sck3 / rts4# / miso3 c7 pb3 cs1# eth1_crs / phyresetout# / txd3 / ctxd1 mclk0 irq3 c8 pb1 mtclka / tclkc eth1_rxer / cts4# c9 pf5 mtioc4a / gtioc1a / tic2 eth1_txen c10 p87 a23 mtioc4c / gtioc1b eth1_txc / eth0_rxd0 mclk1 an1_ane x1 c11 pd6 a22 tic1 eth1_txd2 / eth0_txd1 / miso2 mclk2 an114 c12 p53 eth1_int / miso2 c13 p51 phylink1 / rspck2 irq1 c14 an004 table 1.7 list of pin and pin functions (320-pin fbga) (2 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 36 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. c15 an000 c16 vrefl0 c17 vrefh0 c18 pd2 wait# an110 c19 p14 cas# mtioc4a / gtioc1a c20 p13 ras# mtioc4c / gtioc1b d1 p81 tiocc0 eth0_rxer / cts4# d2 p80 tiocc3 eth0_rxdv / rts4# irq8 d3 pu3 tiocd6 eth2_col / txd3 d18 pd0 cs4# an108 d19 p96 poe0# / poe10# an106 d20 p95 mtclka cts2# irq13 an105 e1 p84 eth0_col / catlinkact1 / rxd4 e2 p82 tiocd3 eth0_txen / eth1_crs / sck4 / rts3# / usb_ovrcur e3 pu1 tioca11 eth2_rxc / sck3 e5 pu0 tioca10 eth2_rxer e6 pl6 tioca9 eth2_rxd3 e7 pl4 eth2_rxd1 irq4 e8 pl2 tioca6 eth2_txen adtrg1 e9 pl0 tiocb9 eth2_txd0 e10 pk7 tiocb7 eth2_txd2 e11 pk6 tiocb6 eth2_txd3 e12 pd5 a21 tic0 eth1_txd3 / eth0_txd0 / ssl20 mclk3 an113 e13 p56 bs# eth1_txer e14 pd4 eth2_int an112 e15 vccq33 e16 pd1 cs1# an109 e18 p97 a25 irq7 adtrg1 / an107 e19 p94 mtclkb rts2# irq4 an104 e20 p93 mtioc1a / tic3 sck2 an103 f1 pc4 tclkh cati2cclk / scl0 f2 p83 eth0_crs / catlinkact0 / txd4 irq11 table 1.7 list of pin and pin functions (320-pin fbga) (3 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 37 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. f3 p85 clkout25m0 / txd4 / sck4 / usb_vbusen irq5 f5 pu4 tiocc9 mii2_mdc / cts3# f8 pl3 tioca7 eth2_rxd0 f9 pl1 tiocb10 eth2_txc f10 pk5 tiocb8 eth2_txd1 f11 pk4 tiocb11 eth2_txer / mosi2_blue f12 p55 a24 ethswsecout irq5 f13 p50 cs1# phylink0 irq8 f14 pd3 phyresetout2# an111 f15 pk2 a23 f16 p90 ras# tioca5 txd4 an100 f18 p92 cs5# toc3 rxd2 an102 f19 p91 cas# txd2 an101 f20 p12 mtioc4b / gtioc2a g1 pu6 tclkf phyresetout# / cts4# g2 pc5 tclkg cati2cdata / sda0 g3 vccq33 g5 pu5 tiocc6 mii2_mdio / rts3# irq13 g6 pm0 clkout25m2 / txd4 g15 pk3 a24 g16 pa7 d31 / a22 mtioc6b / gtioc3b rts2# mclk0 irq7 g18 pa4 d28 / tend2 tioca3 eth1_int / rxd2 mdat1 adtrg0 g19 pa3 d27 / dack2 gtetrg / tioca2 ethswsecout / sck2 mclk2 g20 p11 mtioc4d / gtioc2b irq9 h1 pu7 catirq / rxd4 h2 pm1 catlederr / sck4 h3 p35 nmi h5 errorout h6 vccq33 h8 vdd h9 vdd h10 vdd h11 vdd h12 vdd h13 vss table 1.7 list of pin and pin functions (320-pin fbga) (4 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 38 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. h15 pa6 d30 / a21 gtioc3a cts2# mdat0 irq6 h16 pa5 d29 tioca4 eth0_int / eth1_txer / txd2 mclk1 h18 pa2 d26 / dreq2 mtioc3b / gtioc0a ssl02 mdat2 h19 pk0 cas# po31 h20 pk1 cs5# j1 pm6 po19 catlinkact0 irq6 j2 pm3 po16 catsync0 / catlatch0 j3 pm2 tclke catsync1 / catlatch1 / rts4# j5 tdo p33 j6 trst# j8 vdd j9 vss j10 vss j11 vss j12 vss j13 vdd j15 vccq33 j16 tracedata7 pa1 d25 mtioc3d / gtioc0b miso0 audio_clk / mclk3 j18 tracedata6 pa0 d24 mtioc4a / gtioc1a mosi0_red mdat3 j19 pt7 a22 / dack2 j20 pt6 a21 / dreq2 k1 pm7 po20 catlinkact1 k2 pm5 po18 catledster k3 pm4 po17 catledrun k5 tdi p34 k6 pllvdd1 k8 vdd k9 vss k10 vss k11 vss k12 vss k13 vdd k15 vss k16 tracedata5 p77 d23 mtioc4c / gtioc1b rspck0 k18 tracedata4 p76 d22 mtioc4b / gtioc2a ssl01 ssiws0 table 1.7 list of pin and pin functions (320-pin fbga) (5 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 39 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. k19 tracedata3 p75 d21 mtioc4d / gtioc2b ssl00 irq13 k20 pt5 bs# / tend2 po30 l1 md1 l2 md2 l3 tms l5 tck l6 pllvss1 l8 vdd l9 vss l10 vss l11 vss l12 vss l13 vdd l15 vss l16 tracedata7 pe7 d15 mtioc7a / tiocd3 / poe8# sck1 / rspck0 l18 tracedata0 p72 d18 mtioc1a / tic2 txd1 ssitxd0 l19 tracedata1 p73 d19 mtclkb rxd1 ssirxd0 irq3 l20 tracedata2 p74 d20 mtclka cts1# / ssl03 ssisck0 m1 xtal m2 extal m3 oscth m5 bscanp m6 pllvdd0 m8 vdd m9 vss m10 vss m11 vss m12 vss m13 vdd m15 vccq33 m16 tracedata6 pe6 d14 mtioc0a / tiocd0 rxd1 / miso0 irq6 m18 traceclk p70 d16 mtioc6d rts1# / usb_ovrcur irq0 m19 pt4 cs3# po29 m20 tracectl p71 d17 / d7 poe0# / poe10# / toc2 sck1 n1 vss n2 md0 n3 rstout# n5 res# n6 pllvss0 table 1.7 list of pin and pin functions (320-pin fbga) (6 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 40 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. n8 vdd n9 vss n10 vdd n11 vdd n12 vdd n13 vdd n15 tracedata2 pe2 d10 mtclkc / tiocb4 ssl02 irq2 n16 tracedata4 pe4 d12 mtioc0b / tiocc0 rts1# / ssl00 n18 tracedata5 pe5 d13 mtioc0c / tiocc3 txd1 / mosi0_blue n19 pt2 tioca1 / tiocb1 / po27 n20 pt3 tioca0 / tiocb0 / po28 cts2# irq11 p1 vss_usb p2 vdd33_usb p3 usb_rref p5 p31 usb_vbusen p6 vccq33 p15 p06 d6 mtioc2b / tiocb0 p16 p07 d7 mtioc2a / tiocb1 p18 tracedata3 pe3 d11 mtioc0d / tiocb5 cts1# / ssl01 irq3 p19 pt0 refout# / irqout# tioca3 / tiocb3 / po25 sck2 irq0 p20 pt1 tioca2 / tiocb2 / po26 rts2# r1 usb_dp r2 usb_dm r3 p30 crxd0 / usb_vbusin r5 pn0 mtioc8d ssl10 r6 pn2 mtioc8b mosi1_blue irq10 r7 pg0 a1 po2 r8 pg2 a3 / we0#/ dqmll po4 / toc0 rspck1 r9 pg7 a8 po9 r10 ph2 a11 mtioc2a / po12 r11 ph4 a13 po14 irq4 r12 ph6 a15 mtioc7d rts0# r13 p23 a0 / dack1 mtic5u txd0 r14 p27 a20 / d4 mtioc8c / tiocb0 rts0# r15 p47 we3#/ dqmuu/ ah# mtioc6c r16 vccq33 r18 vccq33 table 1.7 list of pin and pin functions (320-pin fbga) (7 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 41 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. r19 ps6 breq# tioca5 / tiocb5 / po23 rxd2 irq14 r20 ps7 back# tioca4 / tiocb4 / po24 txd2 t1 dvdd_usb t3 p32 usb_ovrcur irq10 t5 pc6 dreq0 tclkc scl1 / crxd0 / usb_vbusin t6 p37 we1#/ dqmlu po1 t7 p36 we0#/ dqmll po0 t8 pg3 a4 / a1 po5 / tic1 miso1 t9 pg6 a7 / d3 tclkb / po8 ssl11 t10 ph3 a12 mtioc1b / po13 t11 vccq33 t12 ph5 a14 po15 t14 p26 a19 / dreq1 mtioc8d t19 tracedata0 pe0 d8 mtioc1b / tiocb2 t20 tracedata1 pe1 d9 mtclkd / tiocb3 ssl03 u1 p60 tend0 ctxd0 / spbssl u2 p63 spbmo/spbio0 u3 pn1 mtioc8c / po21 miso1 u18 tracectl p00 d0 mtioc6a / tioca1 adtrg1 u19 p04 d4 mtioc3c / tioca5 u20 p03 d3 mtic5u / tioca4 v1 p61 dack0 ctxd1 / spbio3 v2 p64 spbmi/spbio1 v3 pn3 mtioc8a rspck1 v4 pn4 mtioc6c / tiocc6 ssl11 irq12 v5 pc7 tic0 sda1 / crxd1 v6 pg1 a2 po3 v7 pg4 a5 / d1 po6 / toc1 mosi1_red v8 pg5 a6 / d2 tclka / po7 ssl10 v9 ph0 a9 po10 v10 ph1 a10 mtioc2b / po11 v11 ph7 a16 mtic5w v12 p20 a17 mtclkd v13 p21 cs0# mtic5v / tiocb1 cts0# irq1 v15 p45 cs2# v16 p46 cke v17 ps2 mtioc7c ssiws0 v18 p05 d5 mtioc3a v19 p01 d1 mtic5w / tioca2 table 1.7 list of pin and pin functions (320-pin fbga) (8 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 42 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. v20 p02 d2 mtic5v / tioca3 w1 p62 spbclk w2 p65 dreq0 spbio2 w3 pn5 mtioc6a / tiocd9 irq5 w4 pn6 mtioc3c / tiocc9 mclk3 w5 pp0 tend0 poe8# mclk2 w6 pp2 mtioc0c / tclkh mclk1 w7 pp4 mtioc0a mclk0 w8 tracectl pp6 tioca11 rxd1 w9 traceclk pp7 dack1 tclkf / tclkh sck1 w10 tracedata1 pr1 tend1 poe4# cts1# irq9 w11 tracedata3 pr3 tioca10 / tiocb10 w12 tracedata5 pr5 tioca8 / tiocb8 w13 p24 rd/wr# rxd0 irq12 w14 p22 rd# mtioc7b / tiocd0 sck0 irq2 w15 p44 wait# tclkd cts0# irq12 adtrg0 w16 p43 we2#/ dqmul mtioc8b usb_vbusen w17 ps1 mtioc7b ssisck0 irq1 w18 ps3 mtioc7a ssirxd0 w19 ps4 mtioc6d ssitxd0 w20 ps5 mtioc6b y1 vss y2 p67 tend0 gtioc3b ctxd0 / usb_ovrcur irq15 y3 p66 dack0 gtioc3a ctxd1 / usb_vbusen irq14 y4 pn7 dreq0 mtioc3a / tiocd6 mdat3 y5 pp1 dack0 mtioc0d mdat2 y6 pp3 mtioc0b / tclkc mdat1 y7 pp5 po22 mdat0 y8 vss y9 tracedata0 pr0 dreq1 tclke / tclkg txd1 y10 tracedata2 pr2 tioca11 / tiocb11 rts1# y11 tracedata4 pr4 tioca9 / tiocb9 y12 tracedata6 pr6 tioca7 / tiocb7 y13 tracedata7 pr7 tioca6 / tiocb6 y14 p25 a18 / tend1 mtclkc y15 p41 bs# sck0 y16 p42 d5 mtioc7c rxd0 y17 p40 d6 mtioc8a txd0 y18 ps0 mtioc7d audio_clk y19 traceclk p10 ckio tioca0 irq0 table 1.7 list of pin and pin functions (320-pin fbga) (9 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 43 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. note 1. only included in products incorporating an r-in engine y20 vss table 1.7 list of pin and pin functions (320-pin fbga) (10 / 10) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 320-pin fbga (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 44 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. table 1.8 list of pin and pin functions (176-pin hlqfp) (1 / 6) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 176-pin hlqfp (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif) 1 pc3 eth0_rxc / eth0_rxdv / cati2cclk / rxd4 / scl0 / crxd1 2vccq33 3 vss 4vdd 5 p82 tiocd3 eth0_txen / eth1_crs / sck4 / rts3# / usb_ovrcur 6 p85 clkout25m0 / txd4 / sck4 / usb_vbusen irq5 7 errorout 8p35 nmi 9trst# 10 tdo p33 11 tdi p34 12 tms 13 tck 14 bscanp 15 vdd 16 vss 17 md2 18 md1 19 pllvdd1 20 pllvss1 21 oscth 22 vccq33 23 extal 24 xtal 25 vss 26 md0 27 pllvdd0 28 pllvss0 29 res# 30 rstout# 31 vdd 32 vss 33 vdd33_usb 34 vss_usb
r01ds0228ej0060 rev.0.60 page 45 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 35 usb_rref 36 usb_dm 37 usb_dp 38 vdd33_usb 39 dvdd_usb 40 p30 crxd0 / usb_vbusin 41 p60 tend0 ctxd0 / spbssl 42 p61 dack0 ctxd1 / spbio3 43 vccq33 44 p62 spbclk 45 vss 46 p63 spbmo/spbio0 47 p64 spbmi/spbio1 48 p65 dreq0 spbio2 49 vss 50 vdd 51 p36 we0#/ dqmll po0 52 p37 we1#/ dqmlu po1 53 pg0 a1 po2 54 pg1 a2 po3 55 vccq33 56 pg2 a3 / we0#/ dqmll po4 / toc0 rspck1 57 pg3 a4 / a1 po5 / tic1 miso1 58 pg4 a5 / d1 po6 / toc1 mosi1_red 59 pg5 a6 / d2 tclka / po7 ssl10 60 pg6 a7 / d3 tclkb / po8 ssl11 61 pg7 a8 po9 62 ph0 a9 po10 63 ph1 a10 mtioc2b / po11 64 ph2 a11 mtioc2a / po12 65 ph3 a12 mtioc1b / po13 66 vdd 67 vss 68 ph4 a13 po14 irq4 69 ph5 a14 po15 70 ph6 a15 mtioc7d rts0# 71 ph7 a16 mtic5w 72 p24 rd/wr# rxd0 irq12 table 1.8 list of pin and pin functions (176-pin hlqfp) (2 / 6) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 176-pin hlqfp (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 46 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 73 p21 cs0# mtic5v / tiocb1 cts0# irq1 74 p22 rd# mtioc7b / tiocd0 sck0 irq2 75 p23 a0 / dack1 mtic5u txd0 76 p20 a17 mtclkd 77 p25 a18 / tend1 mtclkc 78 p26 a19 / dreq1 mtioc8d 79 p27 a20 / d4 mtioc8c / tiocb0 rts0# 80 vdd 81 vss 82 p42 d5 mtioc7c rxd0 83 p40 d6 mtioc8a txd0 84 p43 we2#/ dqmul mtioc8b usb_vbusen 85 p47 we3#/ dqmuu/ah# mtioc6c 86 vccq33 87 traceclk p10 ckio tioca0 irq0 88 vss 89 tracectl p00 d0 mtioc6a / tioca1 adtrg1 90 p01 d1 mtic5w / tioca2 91 p02 d2 mtic5v / tioca3 92 vccq33 93 p03 d3 mtic5u / tioca4 94 p04 d4 mtioc3c / tioca5 95 p05 d5 mtioc3a 96 p06 d6 mtioc2b / tiocb0 97 p07 d7 mtioc2a / tiocb1 98 tracedata 0 pe0 d8 mtioc1b / tiocb2 99 tracedata 1 pe1 d9 mtclkd / tiocb3 ssl03 100 vss 101 tracedata 2 pe2 d10 mtclkc / tiocb4 ssl02 irq2 102 tracedata 3 pe3 d11 mtioc0d / tiocb5 cts1# / ssl01 irq3 103 tracedata 4 pe4 d12 mtioc0b / tiocc0 rts1# / ssl00 table 1.8 list of pin and pin functions (176-pin hlqfp) (3 / 6) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 176-pin hlqfp (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 47 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 104 tracedata 5 pe5 d13 mtioc0c / tiocc3 txd1 / mosi0_blue 105 tracedata 6 pe6 d14 mtioc0a / tiocd0 rxd1 / miso0 irq6 106 tracedata 7 pe7 d15 mtioc7a / tiocd3 / poe8# sck1 / rspck0 107 vss 108 vdd 109 traceclk p70 d16 mtioc6d rts1# / usb_ovrcur irq0 110 tracectl p71 d17 / d7 poe0# / poe10# / toc2 sck1 111 tracedata 0 p72 d18 mtioc1a / tic2 txd1 ssitxd0 112 tracedata 1 p73 d19 mtclkb rxd1 ssirxd0 irq3 113 tracedata 2 p74 d20 mtclka cts1# / ssl03 ssisck0 114 tracedata 3 p75 d21 mtioc4d / gtioc2b ssl00 irq13 115 tracedata 4 p76 d22 mtioc4b / gtioc2a ssl01 ssiws0 116 tracedata 5 p77 d23 mtioc4c / gtioc1b rspck0 117 tracedata 6 pa0 d24 mtioc4a / gtioc1a mosi0_red mdat3 118 tracedata 7 pa1 d25 mtioc3d / gtioc0b miso0 audio_clk / mclk3 119 vss 120 vdd 121 pa2 d26 / dreq2 mtioc3b / gtioc0a ssl02 mdat2 122 pa3 d27 / dack2 gtetrg / tioca2 ethswsecout / sck2 mclk2 123 pa4 d28 / tend2 tioca3 eth1_int / rxd2 mdat1 adtrg0 124 pa5 d29 tioca4 eth0_int / eth1_txer / txd2 mclk1 125 pa6 d30 / a21 gtioc3a cts2# mdat0 irq6 126 vccq33 127 pa7 d31 / a22 mtioc6b / gtioc3b rts2# mclk0 irq7 128 vdd 129 vss 130 p13 ras# mtioc4c / gtioc1b table 1.8 list of pin and pin functions (176-pin hlqfp) (4 / 6) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 176-pin hlqfp (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 48 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. 131 p14 cas# mtioc4a / gtioc1a 132 p15 cs3# / cke mtioc3d / gtioc0b 133 p16 cs4# / cs2# mtioc3b / gtioc0a 134 p17 cs5# eth1_txer / phyresetout# adtrg0 135 vccq33 136 vrefh0 137 vrefl0 138 avss0 139 avcc0 140 an000 141 an001 142 an002 143 an003 144 an004 145 an005 146 an006 147 an007 148 vdd 149 vss 150 p51 phylink1 / rspck2 irq1 151 p54 clkout25m1 / mosi2_red 152 p56 bs# eth1_txer 153 pd5 a21 tic0 eth1_txd3 / eth0_txd0 / ssl20 mclk3 154 pd6 a22 tic1 eth1_txd2 / eth0_txd1 / miso2 mclk2 155 pd7 mtioc4d / gtioc2b / toc0 eth1_txd1 156 p86 mtioc4b / gtioc2a / toc1 eth1_txd0 / rspck2 157 p87 a23 mtioc4c / gtioc1b eth1_txc / eth0_rxd0 mclk1 158 pf5 mtioc4a / gtioc1a / tic2 eth1_txen 159 vccq33 160 vdd 161 vss table 1.8 list of pin and pin functions (176-pin hlqfp) (5 / 6) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 176-pin hlqfp (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
r01ds0228ej0060 rev.0.60 page 49 of 51 nov 14, 2014 rz/t1 group 1. overview under development preliminary document specifications in this document ar e tentative and subject to change. note 1. only included in products incorporating an r-in engine 162 pf6 mtioc3d / gtioc0b / toc2 eth1_rxd0 163 pb7 mtioc3b / gtioc0a / toc3 eth1_rxd1 164 pc0 wait# gtetrg eth1_rxd2 / scl1 mdat3 165 pc1 eth1_rxd3 / phylink0 / sda1 mdat2 irq9 166 pb0 mtclkb / tclkd / tic3 eth1_rxdv 167 pb1 mtclka / tclkc eth1_rxer / cts4# 168 pb2 mtioc1a eth1_rxc / eth0_rxd1 / catsync1 / catlatch1 / ssl30 mdat1 169 vccq33 170 pb3 cs1# eth1_crs / phyresetout# / txd3 / ctxd1 mclk0 irq3 171 pb4 a24 eth1_col / phyresetout# / catsync0 / catlatch0 / rxd3 / mosi3_blue mdat0 172 pb5 tclkb / poe0# / poe10# eth_mdio / cts3# / rspck3 173 vss 174 vdd 175 pb6 tclka eth_mdc / sck3 / rts4# / miso3 176 pc2 eth0_txc / eth1_rxd2 / cati2cdata / sda0 table 1.8 list of pin and pin functions (176-pin hlqfp) (6 / 6) pin number power supply clock system contro i/o port bus timer communication others interrupt s12adc 176-pin hlqfp (mtu3a, gpta, tpua, ppg, poe3, cmtw) (etherc, ecatc* 1 , scifa, rspia, riica, rscan, spibsc, usb) (ssi, dsmif)
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accordance with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as ch aracteristic values , operating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product. general precautions in the handling of mpu/mcu products
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